Summary
Project title: FLAG - FLoating point Arithmetic units for Graphical applications in FPGAs
Financing body: CNCS – UEFISCDI
Project type: PNII – Human Resources – Young Researchers
Project number: PN-II-RU-TE-2011-3-0186
Contract number: 101/2011
Period: Oct. 2011 - Oct. 2014
Abstract: Recent studies indicate that FPGAs provide better watts/flops performance compared to graphical processing units (GPUs). Adding features such as flexibility and high degree of parallelism makes suitable candidates for implementing graphical accelerators on future embedded systems. This project aims at providing floating point (FP) arithmetic support for graphical applications implemented on FPGAs. The major novelty of the proposal consists in the design of high performance FP units using an efficient exploitation of the FPGA arithmetic resources, such as the embedded multipliers or block RAM modules. Thus, dedicated arithmetic units for reconfigurable devices will be provided. Two types of FP operations are targeted: multiply and multiply-accumulate architectures (used for matrix products, vector and matrix products and dot products) and combined division and square roots (used for matrix inversions, euclidean distance computations, etc). These units will be the backbone of dedicated hardware accelerators (for vertex, geometry and pixel shader operations) for these types of applications. Other potential applications, such as those in scientific computing or DSP, may benefit from the developed FP units