Sergiu NIMARĂ
Poziţie academică
Şef lucrări
Grad
Dr. Ing.
Contact birou
Sala B424
(0256 40) 3272
sergiu.nimara (at) cs.upt.ro
Cercetare
- Analiza impactului erorilor transiente pentru circuite CMOS sub-alimentate, la nivele multiple de abstractizare ale unui sistem digital, 2016. Supervizor: Dr. Ing. Mircea POPA
Selecţie publicaţii
- A. Amaricai, S. Nimara, O. Boncalo, J. Chen and E. Popovici, "Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits," 17th Euromicro Conference on Digital System Design (DSD), Verona, 2014, pp. 473-479, doi: 10.1109/DSD.2014.92
- Sergiu Nimara, Alexandru Amaricai, Oana Boncalo, Mircea Popa, “Multi-level simulated fault injection for data-dependent reliability analysis for RTL circuit descriptions,” Advances in Electrical and Computer Engineering (AECE) Journal, vol. 16, issue 1, pp. 93-98, 2016, DOI: 10.4316/AECE.2016.01013
- Alexandru Amaricai et al., "Multi-level probabilistic timing error reliability analysis using a circuit dependent fault map generation," Conference on Design of Circuits and Integrated Systems (DCIS), Estoril, 2015, pp. 1-6. DOI: 10.1109/DCIS.2015.7388580
- S. Nimara, O. Boncalo, A. Amaricai and M. Popa, "FPGA architecture of multi-codeword LDPC decoder with efficient BRAM utilization," 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Kosice, 2016, pp. 1-4, DOI: 10.1109/DDECS.2016.7482452
- A. Amaricai, S. Nimara, O. Boncalo, E. Popovici, "Reliability analysis of memory centric LDPC decoders under probabilistic storage failures", IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2016, DOI: 10.1109/ICECS.2016.7841271